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<span id="openzim-page-title" class="mw-page-title-main"><span class="mw-page-title-main">Inter-processor interrupt</span></span>
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<p>In <a href="Computing" title="Computing">computing</a>, an <b>inter-processor interrupt</b> (<b>IPI</b>), also known as a <i>shoulder tap</i>, is a special type of <a href="Interrupt" title="Interrupt">interrupt</a> by which one <a href="Processor_(computing)" title="Processor (computing)">processor</a> may interrupt another processor in a <a href="Multiprocessor" class="mw-redirect" title="Multiprocessor">multiprocessor</a> system if the interrupting processor requires action from the other processor. Actions that might be requested include:
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<ul><li>Flush <a href="Memory_management_unit" title="Memory management unit">memory management unit</a> caches, such as <a href="Translation_lookaside_buffer" title="Translation lookaside buffer">translation lookaside buffers</a>, on other processors when memory mappings are changed by one processor;</li>
<li>Stop when the system is being shut down by one processor.</li>
<li>Notify an alternate CPU of a malfunction for Alternate CPU Recovery (ACR).</li>
<li>Notify a processor that higher-priority work is available.</li>
<li>Notify a processor of work that cannot be done on all processors due to, e.g.,
<ul><li>asymmetric access to <a href="I/O_channel" class="mw-redirect" title="I/O channel">I/O channels</a><sup id="cite_ref-1" class="reference"><a href="#cite_note-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup></li>
<li>special features on some processors<sup id="cite_ref-2" class="reference"><a href="#cite_note-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup></li></ul></li></ul>
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<div class="mw-heading mw-heading2"><h2 id="Mechanism">Mechanism</h2></div>
<p>The <a href="OS/360_and_successors#M65MP" title="OS/360 and successors">M65MP</a> option of <a href="OS/360_and_successors" title="OS/360 and successors">OS/360</a> used the Direct Control feature of the <a href="IBM_System/360" title="IBM System/360">S/360</a> to generate an interrupt on another processor; on <a href="IBM_System/370" title="IBM System/370">S/370</a> and its successors, including <a href="Z/Architecture" title="Z/Architecture">z/Architecture</a>, the SIGNAL PROCESSOR instruction provides a more formalized interface. The documentation for some IBM operating systems refers to this as a shoulder tap.
</p><p>On <a href="IBM_PC_compatible" title="IBM PC compatible">IBM PC compatible</a> computers that use the <a href="Advanced_Programmable_Interrupt_Controller" title="Advanced Programmable Interrupt Controller">Advanced Programmable Interrupt Controller</a> (APIC), IPI signaling is often performed using the APIC. When a CPU wishes to send an interrupt to another CPU, it stores the <a href="Interrupt_vector" class="mw-redirect" title="Interrupt vector">interrupt vector</a> and the identifier of the target's local APIC in the Interrupt Command Register (ICR) of its own local APIC. A message is then sent via the APIC bus to the target's local APIC, which then issues a corresponding interrupt to its own CPU.
</p>
<div class="mw-heading mw-heading2"><h2 id="Examples">Examples</h2></div>
<p>In a multiprocessor system running <a href="Microsoft_Windows" title="Microsoft Windows">Microsoft Windows</a>, a processor may interrupt another processor for the following reasons, in addition to the ones listed above:<sup id="cite_ref-3" class="reference"><a href="#cite_note-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup>
</p>
<ol><li>queue a DISPATCH_LEVEL interrupt to schedule a particular thread for execution;</li>
<li>kernel debugger breakpoint.</li></ol>
<p>IPIs are given an <a href="IRQL_(Windows)" title="IRQL (Windows)">IRQL</a> of 29.<sup id="cite_ref-4" class="reference"><a href="#cite_note-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup>
</p>
<div class="mw-heading mw-heading2"><h2 id="See_also">See also</h2></div>
<ul><li><a href="Interrupt" title="Interrupt">Interrupt</a></li>
<li><a href="Interrupt_handler" title="Interrupt handler">Interrupt handler</a></li>
<li><a href="Non-maskable_interrupt" title="Non-maskable interrupt">Non-maskable interrupt</a> (NMI)</li></ul>
<div class="mw-heading mw-heading2"><h2 id="References">References</h2></div>
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<li id="cite_note-1"><span class="mw-cite-backlink"><b><a href="#cite_ref-1">^</a></b></span> <span class="reference-text"><style data-mw-deduplicate="TemplateStyles:r1238218222">
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</style><cite class="citation book cs1"><a rel="nofollow" class="external text" href="http://bitsavers.org/pdf/ibm/360/os/R21.7_Apr73/plm/GY28-6616-9_OS_IO_Superv_PLM_R21.7_Apr73.pdf#page=282">"Appendix F: Multiprocessing Extensions"</a> <span class="cs1-format">(PDF)</span>. <a rel="nofollow" class="external text" href="http://bitsavers.org/pdf/ibm/360/os/R21.7_Apr73/plm/GY28-6616-9_OS_IO_Superv_PLM_R21.7_Apr73.pdf"><i>OS I/O Supervisor Logic - Release 21 - Program Number 360S-CI-505</i></a> <span class="cs1-format">(PDF)</span>. Program Logic. <a href="IBM" title="IBM">IBM</a>. p. 271. GY28-6616-9<span class="reference-accessdate">. Retrieved <span class="nowrap">August 28,</span> 2022</span>.</cite></span>
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<li id="cite_note-2"><span class="mw-cite-backlink"><b><a href="#cite_ref-2">^</a></b></span> <span class="reference-text"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://docs.amd.com/r/en-US/am011-versal-acap-trm/Inter-Processor-Interrupts">"AMD Technical Information Portal"</a>. <i>docs.amd.com</i><span class="reference-accessdate">. Retrieved <span class="nowrap">2024-07-18</span></span>.</cite></span>
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<li id="cite_note-3"><span class="mw-cite-backlink"><b><a href="#cite_ref-3">^</a></b></span> <span class="reference-text"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://stackoverflow.com/questions/15091165/inter-processor-interrupt-usage">"Inter Processor Interrupt usage"</a>. <i>Stack Overflow</i><span class="reference-accessdate">. Retrieved <span class="nowrap">2024-07-18</span></span>.</cite></span>
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<li id="cite_note-4"><span class="mw-cite-backlink"><b><a href="#cite_ref-4">^</a></b></span> <span class="reference-text"><cite id="CITEREFMatt2002" class="citation web cs1">Matt (2002-04-28). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20191014125625/http://ext2fsd.sourceforge.net/documents/irql.htm">"Understanding IRQL"</a>. Archived from <a rel="nofollow" class="external text" href="http://ext2fsd.sourceforge.net/documents/irql.htm">the original</a> on 2019-10-14<span class="reference-accessdate">. Retrieved <span class="nowrap">2014-12-06</span></span>.</cite></span>
</li>
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<div class="mw-heading mw-heading2"><h2 id="External_links">External links</h2></div>
<ul><li><a rel="nofollow" class="external text" href="http://linux.linti.unlp.edu.ar/images/0/0c/ULK3-CAPITULO4-UNNOBA.pdf">Interrupts and Exceptions</a></li></ul>
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